Hill-Climbing Chip Design with a Self-Improving Loop

The task

Softmax sits inside every attention layer, and its one transcendental is the exponential. An accelerator team needs that unit small, because an accelerator replicates it many times. So we asked the loop to design a bfloat16 exponential, y = e^x, at the smallest area that still meets the clock.

The rules are strict, and the flow enforces all of them:

• Correct on every input. All 65,536 encodings are simulated on the synthesized netlist: normals, subnormals, both zeros, both infinities and all 254 NaNs. The answer must be correctly rounded (0 ULP error), with ties to even.
• Inside the envelope. At most 4,000 LUT4 equivalents, 16 DSP blocks and 2 block RAMs on a Lattice ECP5, built with yosys, nextpnr and verilator.
• Gated, then scored. A design that misses the clock, latency or area gate scores zero. Among designs that pass, smaller and faster scores higher.

A DSP block costs as much area as 3,000 LUTs, so the score pushes hard against hard multipliers. The task comes in six variants that change the clock, latency, accuracy and resource limits.

Why a coding agent alone falls short

A frontier coding agent can write Verilog and run the tools. Left alone, it still tends to stop at the first design that passes. Each run starts from zero, so what one attempt learns about cheap encodings or where to put a register is lost before the next attempt. The know-how that closes the gap lives in senior designers’ heads, and in the tool reports the agent read once and forgot.

How the loop works

Our loop wraps the same agents and tools in four parts. Each part answers one question that a good design team asks every day.

1. Search planner. Picks the idea most likely to pay off, and spends the next hour of compute where the map is still blank.
2. Experiment controller. Turns an idea into a run with a baseline, and checks whether a gain is real or noise.
3. Research ledger. Records what was tried, what worked, and which tool report proves it. A claim counts only when a tool run backs it.
4. Knowledge base. Supplies design flows, tool documentation, timing rules and lessons from past projects.

A second, slower loop runs on top. The graded runs become training data for an open-weight model, and the stronger model plugs back into the loop.

Results

Every system got the same task, the same tools, and the same grader. On all six variants, the loop reached a higher score than both frontier agents, and usually got there sooner.

The first variant shows the shape of the gap most clearly. The loop reached 29.9 at minute 23. Codex Astra needed about 42 minutes to reach 21.0. We also ran an open-weight model post-trained on the loop’s graded runs: it reached 22.1, ahead of both frontier agents, though still behind the loop.

What the loop built

The winning design uses no multiplier and no hard block at all. It is 377 LUT4s and 24 flip-flops, 401 area units in total, and it runs at 95.95 MHz with one register stage of its own. It is correctly rounded on every one of the 65,536 inputs.

Here is the trick in plain terms. The usual textbook design multiplies the input by log₂e, which needs a multiplier. The loop found that, for 16-bit inputs, the product can be built from two tiny tables added on one carry chain. Rounding, the exponent bias and the final assembly all ride on that same chain. Special inputs such as infinity and NaN load a fixed value into the register, so the second stage needs no extra logic.

A second example: trimming a multiplier

The same behavior shows up on an fp16 exponential tuned for clock speed. Here the loop kept a multiplier but made it narrower. It re-fit the slope coefficients to multiples of 32, which stores 9 bits instead of 14 and shrinks the multiplier from 14×11 to 9×11. The re-fit breaks a few inputs. A small exact-match block corrects those 7 inputs before rounding, so the result stays correctly rounded.

In a local ablation between two versions of the loop, this one idea cut the unit’s area from 1,842 to 1,411, a 23.4% drop.

How to read these numbers

• Each line is a single run. We have not yet repeated runs to measure spread.
• The flow is an open-source FPGA flow on a Lattice ECP5, so anyone can rerun the grader. Area counts LUT4 equivalents and flip-flops, with hard blocks charged at the weights above.
• All systems shared the same harness files: the makefile, scoring and gate scripts, testbench and reference model.
• The post-trained open-weight model passes up to 75% of runs. Its circuits are still larger than the loop’s best, and closing that gap needs more data and compute.

What this means for a chip team

Nothing here is specific to exponentials. The loop needs three things a chip team already has: a spec, a flow that grades a design, and the tools that flow runs. We set the loop up on the team’s own flow, inside its network. The team keeps the graded traces, the benchmark and any trained weights, so each project starts from everything the last one learned.